1. Technical Field
The present invention relates generally to semiconductor technology, and more specifically to semiconductor research and development.
2. Background Art
At the present time, electronic products are used in almost every aspect of life, and the heart of these electronic products is the integrated circuit. Integrated circuits are used in a wide variety of products, such as televisions, telephones, and appliances.
Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each worth hundreds or thousands of dollars.
The ideal would be to have every one of the integrated circuits on a wafer functional and within specifications, but because of the sheer numbers of processes and minute variations in the processes, this rarely occurs. “Yield” is the measure of how many “good” integrated circuits there are on a wafer divided by the maximum number of possible good integrated circuits on the wafer. A 100% yield is extremely difficult to obtain because minor variations, due to such factors as timing, temperature, and materials, substantially affect a process. Further, one process often affects a number of other processes, often in unpredictable ways.
In a manufacturing environment, the primary purpose of experimentation is to increase the yield. Experiments are performed in-line and at the end of the production line with both production wafers and experimental wafers. However, yield enhancement methodologies in the manufacturing environment produce an abundance of very detailed data for a large number of wafers in processes subject only to minor variations. Major variations in the processes are not possible because of the time and cost of using production equipment and production wafers. Setup times for equipment and processing time can range from weeks to months, and processed wafers can each contain hundreds of thousands of dollars worth of integrated circuits.
The learning cycle for the improvement of systems and processes requires coming up with an idea, formulating a test(s) of the idea, testing the idea to obtain data, studying the data to determine the correctness of the idea, and developing new ideas based on the correctness of the first idea. The faster the correctness of ideas can be determined, the faster new ideas can be developed. Unfortunately, the manufacturing environment provides a slow learning cycle because of manufacturing time and cost.
Recently, the great increase in the complexity of integrated circuit manufacturing processes and the decrease in time between new product conception and market introduction have both created the need for speeding up the learning cycle.
This has been accomplished in part by the unique development of the integrated circuit research and development environment. In this environment, the learning cycle has been greatly speeded up and innovative techniques have been developed that have been extrapolated to high volume manufacturing facilities.
To speed up the learning cycle, processes are speeded up and major variations are made to many processes. To reduce costs, only a few wafers are actually processed for each cycle. This research and development environment has resulted in the generation of tremendous amounts of data and analysis for all the different processes and variations. This, in turn, has required a large number of engineers to do the analysis. With more data, the answer always has been to hire more engineers.
However, this is not an acceptable solution for major problems. For example, as the dimensions of individual features of a semiconductor wafer shrink with each new technology generation, it becomes ever more difficult to perform accurate failure analysis tests on the semiconductor devices. This is particularly true of the ever-smaller individual features, such as the distinct conductors and vias, in these devices. It is essential that the tests be performed accurately, easily, and quickly, since semiconductor wafers can each be worth thousands of dollars or more. Production corrections must consequently be made quickly and reliably, as soon as product problems or anomalies are detected.
The first step in resolving such issues is accurately diagnosing the source of the problem. This requires precision testing equipment that can be easily yet accurately and dependably operated. Integrated circuits are typically tested by contacting conductive pads on the semiconductor wafer with a probe unit that is connected to a probe card. The probe card contains the circuitry necessary to perform electrical diagnosis and characterization of the integrated circuits. A traditional probe unit includes “pogo” pins or needles suspended from the body of the probe unit for contacting the electrical pads of the integrated circuits of the wafer. The pins or needles are conductive, and thus, when in proper contact with the pads, provide electrical communication between an integrated circuit being tested and the diagnostic tester circuitry on the probe card.
When such testing reveals a defective chip or die on the wafer, it is sometimes necessary to examine individual features, such as individual metallic conductors or vias, within that die. This often involves removing part of the die structure to expose the interior elements that need to be tested. Sometimes a thin section of the die will be removed for testing. In all such cases, electrical connections must be made to the exposed structures. This can be far more difficult than the initial testing of the intact die, since the internal integrated circuit structures are much, much smaller. Thus, with ever smaller and smaller circuit structures and dimensions, known pad and probe contacts are increasingly proving to be inadequate.
More particularly, the relatively large distance between the contact elements on such pad and probe contacts makes it harder and harder to make proper, reliable contact with very small test points that are arranged in a very tight space. Too often, the test contact elements may contact more than one metallic element on the structure being tested.
A need therefore remains for tester contact structures that can assure accurate and proper connections to very small integrated circuit device structures under test.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.